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16 Mbit LPC Serial Flash
A Microchip Technology Company
SST49LF016C
Data Sheet
Pin Descriptions
Table 1: Pin Description
Interface
Symbol Pin Name
LCLK Clock
LAD[3:0] Address
and Data
LFRAME Frame
#
RST# Reset
INIT# Initialize
ID[3:0] Identification
Inputs
GPI[4:0] General
Purpose
Inputs
Type 1 AAI LPC Functions
I X X To accept a clock input from the control unit
I/O X X To provide LPC bus information, such as addresses and com-
mand Inputs/Outputs data.
I X X To indicate the start of a data transfer operation; also used to
abort an LPC cycle in progress.
I X X To reset the operation of the device
I X X This is the second reset pin for in-system use. This pin is inter-
nally combined with the RST# pin. If this pin or RST# pin is
driven low, identical operation is exhibited.
I X X These four pins are part of the mechanism that allows multiple
parts to be attached to the same bus. The strapping of these
pins is used to identify the component. The boot device must
have ID[3:0]=0000, all subsequent devices should use sequen-
tial up-count strapping. These pins are internally pulled-down
with a resistor between 20-100 K ? . When in AAI mode, these
pins operate identically as in Firmware Memory cycles.
I X These individual inputs can be used for additional board flexibility.
The state of these pins can be read through LPC registers. These
inputs should be at their desired state before the start of the LPC
clock cycle during which the read is attempted, and should rem ain
in place until the end of the Read cycle. Unused GPI pins must not
be floated. GPI[2:4] are ignored when in AAI mode.
TBL# Top Block Lock I X When low, prevents programming to the boot block sectors at
top of device memory. When TBL# is high it disables hardware
write protection for the top block sectors. This pin cannot be left
unconnected. TBL# setting is ignored when in AAI mode.
WP#/AAI Write Protect I X
When low, prevents programming to all but the highest addressable
block (Boot Block). When WP# is high it disables hardware write
protection for these blocks. This pin cannot be left unconnected.
WP#/AAI AAI Enable I X When set to the Supervoltage V H = 9V, configures the device to
program multiple bytes in AAI mode. When brought to V IL /V IH ,
returns device to LPC mode.
RY/BY# Ready/Busy# O X Open drain output that indicates the device is ready to accept
data in an AAI mode, or that the internal cycle is complete.
Used in conjunction with LD# pin to switch between these two
flag states.
LD# Load-Enable# I X Input pin which when low, indicates the host is loading data in
an AAI programming cycle. If LD# is high, the host signals the
AAI interface that it is terminating a command. LD# low/high
switches the RY/BY# output from a “buffer free” flag to a “pro-
gramming complete” flag.
V DD
V SS
Power Supply PWR X X To provide power supply (3.0-3.6V)
Ground PWR X X Circuit ground (0V reference)
NC No Connection N/A N/A Unconnected pins.
T1.2 25029
1. I=Input, O=Output
?2011 Silicon Storage Technology, Inc.
7
DS25029A
06/11
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